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philips semiconductors pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt product data 2003 jun 27 integrated circuits
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2 2003 jun 27 features ? operating power supply voltage range of 2.3 v-5.5 v ? 5 v tolerant i/os ? polarity inversion register ? active low interrupt output ? low stand-by current ? noise filter on scl/sda inputs ? no glitch on power-up ? internal power-on reset ? 16 i/o pins which default to 16 inputs ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jesdec standard jesd78 which exceeds 100 ma ? offered in three different packages: so24, tssop24, and hvqfn24 description the pca9535 is a 24-pin cmos device that provide 16 bits of general purpose parallel input/output (gpio) expansion for i 2 c/smbus applications and was developed to enhance the philips family of i 2 c i/o expanders. the improvements include higher drive capability, 5 v i/o tolerance, lower supply current, individual i/o configuration, and smaller packaging. i/o expanders provide a simple solution when additional i/o is needed for acpi power switches, sensors, pushbuttons, leds, fans, etc. the pca9535 consist of two 8-bit configuration (input or output selection); input, output and polarity inversion (active high or active low operation) registers. the system master can enable the i/os as either inputs or outputs by writing to the i/o configuration bits. the data for each input or output is kept in the corresponding input or output register. the polarity of the read register can be inverted with the polarity inversion register. all registers can be read by the system master. although pin-to-pin and i 2 c address compatible with the pcf8575, software changes are required due to the enhancements and are discussed in application note an469. the pca9535 is identical to the pca9555 except for the removal of the internal i/o pull-up resistor which greatly reduces power consumption when the i/os are held low. the pca9535 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. the power-on reset sets the registers to their default values and initializes the device state machine. three hardware pins (a0, a1, a2) vary the fixed i 2 c address and allow up to eight devices to share the same i 2 c/smbus. the fixed i 2 c address of the pca9535 is the same as the pca9554 allowing up to eight of these devices in any combination to share the same i 2 c/smbus. ordering information packages temperature range order code topside mark drawing number 24-pin plastic so -40 to +85 c pca9535d pca9535d sot137-1 24-pin plastic tssop -40 to +85 c pca9535pw pca9535pw sot355-1 24-pin plastic hvqfn -40 to +85 c pca9535bs 9535 sot616-1 standard packing quantities and other packing data are available at www.philipslogic.com/packaging . i 2 c is a trademark of philips semiconductors corporation. smbus as specified by the smart battery system implementers forum is a derivative of the philips i 2 c patent.
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 3 pin configuration ? so, tssop su01438 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 int a1 a2 i/o0.0 i/o0.1 i/o0.2 i/o0.3 i/o0.4 i/o0.5 i/o0.6 i/o0.7 v dd sda scl a0 i/o1.7 i/o1.6 i/o1.5 i/o1.3 i/o1.4 i/o1.2 i/o1.1 i/o1.0 v ss figure 1. pin configuration ? so, tssop pin configuration ?hvqfn 18 17 16 15 14 7 8 9 10 11 1 2 3 4 5 24 23 22 21 20 su01683 top view i/o0.0 a0 6 13 12 19 i/o0.1 i/o0.2 i/o0.3 i/o0.4 i/o0.5 i/o1.3 i/o1.4 i/o1.5 i/o1.6 i/o1.7 i/o0.6 i/o0.7 i/o1.0 i/o1.1 i/o1.2 a2 a1 int v sda scl dd v ss figure 2. pin configuration ? hvqfn pin description so, tssop pin number hvqfn pin number symbol function 1 22 int interrupt output (open drain) 2 23 a1 address input 1 3 24 a2 address input 2 4-1 1 1-8 i/o0.0-i/o0.7 i/o0.0 to i/o0.7 12 9 v ss supply ground 13-20 10-17 i/o1.0-i/o1.7 i/o1.0 to i/o1.7 21 18 a0 address input 0 22 19 scl serial clock line 23 20 sda serial data line 24 21 v dd supply voltage
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 4 block diagram power-on reset input filter i 2 c/smbus control input/ output ports write pulse read pulse a0 a1 a2 scl sda v dd v ss 8-bit i/o0.0 i/o0.1 i/o0.2 i/o0.3 i/o0.4 i/o0.5 i/o0.6 i/o0.7 su01439 note: all i/os are set to inputs at reset v int int 8-bit input/ output ports i/o1.0 i/o1.1 i/o1.2 i/o1.3 i/o1.4 i/o1.5 i/o1.6 i/o1.7 write pulse read pulse lp filter figure 3. block diagram
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 5 simplified schematic of i/os write pulse data from shift register v dd i/o pin v ss write configuration pulse d c k ff q d c k q ff d c k q ff d c k q ff input port register polarity inversion register output port register data from shift register data from shift register write polarity pulse configuration register output port register data input port register data polarity register data read pulse su01682 q q q q to int q1 q2 note: at power-on reset, all registers return to default values. figure 4. simplified schematic of i/os i/o port when an i/o is configured as an input, fets q1 and q2 are off, creating a high impedance input. the input voltage may be raised above v dd to a maximum of 5.5 v. if the i/o is configured as an output, then either q1 or q2 is on, depending on the state of the output port register. care should be exercised if an external voltage is applied to an i/o configured as an output because of the low impedance path that exists between the pin and either v dd or v ss .
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 6 registers command byte command register 0 input port 0 1 input port 1 2 output port 0 3 output port 1 4 polarity inversion port 0 5 polarity inversion port 1 6 configuration port 0 7 configuration port 1 the command byte is the first byte to follow the address byte during a write transmission. it is used as a pointer to determine which of the following registers will be written or read. registers 0 and 1 ? input port registers this register is an input-only port. it reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by register 3. writes to this register have no effect. registers 2 and 3 ? output port registers bit o0.7 o0.6 o0.5 o0.4 o0.3 o0.2 o0.1 o0.0 default 1 1 1 1 1 1 1 1 bit o1.7 o1.6 o1.5 o1.4 o1.3 o1.2 o1.1 o1.0 default 1 1 1 1 1 1 1 1 this register is an output-only port. it reflects the outgoing logic levels of the pins defined as outputs by register 6 and 7. bit values in this register have no effect on pins defined as inputs. in turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. registers 4 and 5 ? polarity inversion registers bit n0.7 n0.6 n0.5 n0.4 n0.3 n0.2 n0.1 n0.0 default 0 0 0 0 0 0 0 0 bit n1.7 n1.6 n1.5 n1.4 n1.3 n1.2 n1.1 n1.0 default 0 0 0 0 0 0 0 0 this register allows the user to invert the polarity of the input port register data. if a bit in this register is set (written with ?1?), the input port data polarity is inverted. if a bit in this register is cleared (written with a ?0?), the input port data polarity is retained. registers 6 and 7 ? configuration registers bit c0.7 c0.6 c0.5 c0.4 c0.3 c0.2 c0.1 c0.0 default 1 1 1 1 1 1 1 1 bit c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 default 1 1 1 1 1 1 1 1 this register configures the directions of the i/o pins. if a bit in this register is set (written with ?1?), the corresponding port pin is enabled as an input with high impedance output driver. if a bit in this register is cleared (written with ?0?), the corresponding port pin is enabled as an output. at reset the device?s ports are inputs. power-on reset when power is applied to v dd , an internal power-on reset holds the pca9535 in a reset state until v dd has reached v por . at that point, the reset condition is released and the pca9535 registers and smbus state machine will initialize to their default states. device address 0 1 0 0a2a1a0 slave address su01441 fixed programmable r/w figure 5. pca9535 address bus transactions writing to the port registers data is transmitted to the pca9535 by sending the device address and setting the least significant bit to a logic 0 (see figure 5 for device address). the command byte is sent after the address and determines which register will receive the data following the command byte. the eight registers within the pca9535 are configured to operate as four register pairs. the four pairs are input ports, output ports, polarity inversion ports, and configuration ports. after sending data to one register, the next data byte will be sent to the other register in the pair (see figures 6 and 7). for example, if the first byte is sent to output port (register 3), then the next byte will be stored in output port 0 (register 2). there is no limitation on the number of data bytes sent in one write transmission. in this way, each 8-bit register may be updated independently of the other registers. reading the port registers in order to read data from the pca9535, the bus master must first send the pca9535 address with the least significant bit set to a logic 0 (see figure 5 for device address). the command byte is sent after the address and determines which register will be accessed. after a restart, the device address is sent again but this time, the least significant bit is set to a logic 1. data from the register defined by the command byte will then be sent by the pca9535 (see figures 8 , 9, and 10). data is clocked into the register on the falling edge of the acknowledge clock pulse. after the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. for example, if you read input port 1, then the next byte read would be input port 0. there is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. interrupt output the open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. the interrupt is deactivated when the input returns to its previous state or the input port register is read (see figure 9). a pin configured as an output cannot cause an interrupt. since each 8-bit port is read independently, the interrupt caused by port 0 will not be cleared by a read of port 1 or the other way around. note that changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register.
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 7 2003 jun 27 12 scl write to port data out from port 0 345678 sda aa a data 0 slave address data to port 0 start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave t pv su01442 9 0 0000001 command byte 0.7 0.0 data 1 1.7 1.0 a data to port 1 s 0 1 0 0 a2 a1 a0 0 data out from port 1 data valid t pv p figure 6. write to output port registers 12 scl 345678 sda aa a data 0 slave address data to register start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave su01443 9 0 0000011 command byte msb lsb data 1 msb lsb a data to register s 0 1 0 0 a2 a1 a0 0 12345 6789 123456789 123 45 p figure 7. write to configuration registers
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 8 2003 jun 27 1 0 a2 a1 a0 0 0 0 0 a2 a1 a0 0 1 s0a a a command byte acknowledge from slave r/w acknowledge from slave a p na acknowledge from slave acknowledge from master s data data r/w first byte at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter last byte su01463 no acknowledge from master 1 slave address data from upper or lower byte of register data from lower or upper byte of register slave address msb lsb msb lsb note: transfer can be stopped at any time by a stop condition. figure 8. read from register 123456789 s0100 a2 a1 a0 1 a 76543210 a i0.x 76543210 a i1.x 7 6543210 a i0.x 76543210 1 i1.x p r/w acknowledge from slave scl sda acknowledge from master acknowledge from master acknowledge from master non acknowledge from master read from port 0 data into port 0 read from port 1 data into port 1 int t ir t iv su01464 notes: transfer of data can be stopped at any moment by a stop condition. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previously been set to 00 (read input port port register). figure 9. read input port register ? scenario 1
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 9 2003 jun 27 123456789 s0100 a2 a1 a0 1 a a i0.x a i1.x a i0.x 1 i1.x p r/w acknowledge from slave scl sda acknowledge from master acknowledge from master acknowledge from master non acknowledge from master read from port 0 data into port 0 read from port 1 data into port 1 int t ir t iv su01651 t ph data 00 data 10 data 03 data 12 data 00 data 01 data 02 data 03 t ps t ph t ps data 10 data 11 data 12 notes: transfer of data can be stopped at any moment by a stop condition. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previously been set to 00 (read input port port register). figure 10. read input port register ? scenario 2
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 10 typical application sw02094 i/o 0.0 i/o 0.1 i/o 0.2 i/o 0.3 i/o 0.4 i/o 0.5 v dd v dd scl sda int reset master controller gnd scl sda pca9535 a2 a1 a0 v ss v dd subsystem 3 (e.g. alarm system) subsystem 2 (e.g. counter) subsystem 1 (e.g. temp sensor) int v dd alarm controlled switch (e.g. cbt device) enable 1.6 k ? 1.6 k ? 1.1 k ? 2 k ? note: device address configured as 0100100 for this example i/o 0.0 , i/o 0.1 , i/o 0.2 , configured as outputs i/o 0.3 , i/o 0.4 , i/o 0.5 , configured as inputs i/o 0.6 , i/o 0.7 , and i/o 1.0 to i/o 1.7 configured as inputs a b 2 k ? int i/o 0.6 i/o 0.7 i/o 1.0 i/o 1.1 i/o 1.2 i/o 1.3 i/o 1.4 i/o 1.5 i/o 1.6 i/o 1.7 10 digit numeric keypad figure 11. typical application minimizing i dd when the i/o is used to control leds when the i/os are used to control leds, they are normally connected to v dd through a resistor as shown in figure 11. since the led acts as a diode, when the led is off the i/o v in is about 1.2 v less than v dd . the supply current, i dd , increases as v in becomes lower than v dd and is specified as ? i dd in the dc characteristics table. designs needing to minimize current consumption, such as battery power applications, should consider maintaining the i/o pins g reater than or equal to v dd when the led is off. figure 12 shows a high value resistor in parallel with the led. figure 13 shows v dd less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v in at or above v dd and prevents additional supply current consumption when the led is off. v dd v dd ledx led 100 k sw02086 figure 12. high value resistor in parallel with the led v dd 3.3 v ledx led sw02087 5 v figure 13. device supplied by a lower voltage
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 11 absolute maximum ratings in accordance with the absolute maximum rating system (iec 134) symbol parameter conditions min max unit v dd supply voltage -0.5 6.0 v v i/o dc input current on an i/o v ss - 0.5 6 v i i/o dc output current on an i/o ? 50 ma i i dc input current ? 20 ma i dd supply current ? 160 ma i ss supply current ? 200 ma p tot total power dissipation ? 200 mw t stg storage temperature range -65 +150 c t amb operating ambient temperature -40 +85 c
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 12 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirab le to take precautions appropriate to handling mos devices. advice can be found in data handbook ic24 under ? handling mos devices ? . dc characteristics v dd = 2.3 to 5.5 v; v ss = 0 v; t amb = -40 to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 ? 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; f scl = 100 khz; i/o = inputs ? 135 200 a i stbl standby current standby mode; v dd = 5.5 v; no load; v i = v ss ; f scl = 0 khz; i/o = inputs ? 0.25 1 a i stbh standby current standby mode; v dd = 5.5 v; no load; v i = v dd ; f scl = 0 khz; i/o = inputs ? 0.25 1 a v por power-on reset voltage no load; v i = v dd or v ss ? 1.5 1.65 v input scl; input/output sda v il low-level input voltage -0.5 ? 0.3 v dd v v ih high-level input voltage 0.7 v dd ? 5.5 v i ol low-level output current v ol = 0.4v 3 ? ? ma i l leakage current v i = v dd = v ss -1 ? +1 a c i input capacitance v i = v ss ? 6 10 pf i/os v il low-level input voltage -0.5 ? 0.8 v v ih high-level input voltage 2.0 ? 5.5 v v ol = 0.5 v; v dd = 2.3-5.5 v; note 1 8 8-20 ? ma i ol low-level output current v ol = 0.7 v; v dd = 2.3-5.5 v; note 1 10 10-24 ? ma i oh = -8 ma; v dd = 2.3 v; note 2 1.8 ? ? v i oh = -10 ma; v dd = 2.3 v; note 2 1.7 ? ? v i oh = -8 ma; v dd = 3.0 v; note 2 2.6 ? ? v v oh high-level output voltage i oh = -10 ma; v dd = 3.0 v; note 2 2.5 ? ? v i oh = -8 ma; v dd = 4.75 v; note 2 4.1 ? ? v i oh = -10 ma; v dd = 4.75 v; note 2 4.0 ? ? v i ih input leakage current v dd = 5.5 v; v i = v dd ? ? 1 a i il input leakage current v dd = 5.5 v; v i = v ss ? ? -1 a c i input capacitance ? 3.7 5 pf c o output capacitance ? 3.7 5 pf interrupt int i ol low-level output current v ol = 0.4 v 3 ? ? ma select inputs a0, a1, a2 v il low-level input voltage -0.5 ? 0.8 v v ih high-level input voltage 2.0 ? 5.5 v i li input leakage current -1 ? 1 a notes: 1. the total current sunk by all i/os must be limited to 200 ma. 2. the total current sourced by all i/os must be limited to 160 ma.
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 13 sda scl su01469 t hd;sta t f s t low t r t hd;dat t su;dat t high t f t su;sta s r t hd;sta t sp t su;std p t r t buf s figure 14. definition of timing ac characteristics symbol parameter standard mode i 2 c bus fast mode i 2 c bus units symbol parameter min max min max units f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start conditions 4.7 ? 1.3 ? s t hd;sta hold time after (repeated) start condition 4.0 ? 0.6 ? s t su;sta repeated start condition setup time 4.7 ? 0.6 ? s t su;sto set-up time for stop condition 4.0 ? 0.6 ? s t vd;ack valid time of ack condition 2 0.3 3.45 0.1 0.9 s t hd;dat data in hold time 0 ? 0 ? ns t vd;dat data out valid time 3 300 ? 50 ? ns t su;dat data set-up time 250 ? 100 ? ns t low clock low period 4.7 ? 1.3 ? s t high clock high period 4.0 ? 0.6 ? s t f clock/data fall time ? 300 20 + 0.1c b 1 300 ns t r clock/data rise time ? 1000 20 + 0.1c b 1 300 ns t sp pulse width of spikes that must be suppressed by the input filters ? 50 ? 50 ns port timing t pv output data valid ? 200 ? 200 ns t ps input data set-up time 150 ? 150 ? ns t ph input data hold time 1 ? 1 ? s interrupt timing t iv interrupt valid ? 4 ? 4 s t ir interrupt reset ? 4 ? 4 s notes: 1. c b = total capacitance of one bus line in pf. 2. t vd;ack = time for acknowledgement signal from scl low to sda (out) low. 3. t vd;dat = minimum time for sda data out to be valid following scl low. 4. t pv measured from 0.7v dd on scl to 50% i/o output.
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 14 pulse generator v in d.u.t. v out c l v dd test circuit for outputs r t r l su01760 definitions r l =1 k ? c l = 50 pf r t = termination resistance should be equal to z out of pulse generators. figure 15. t pv set - up conditions
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 15 so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 16 tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 17 hvqfn24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm sot616-1
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 18 revision history rev date description _1 20030627 product data (9397 750 11681); ecn 853-2430 30019 dated 11 june 2003. initial version
philips semiconductors product data pca9535 16-bit i 2 c and smbus, low power i/o port with interrupt 2003 jun 27 19 purchase of philips i 2 c components conveys a license under the philips ? i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products ? including circuits, standard cells, and/or software ? described or contained herein in order to improve design and/or performance. when the product is in full production (status ? production ? ), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 06-03 document order number: 9397 750 11681 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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